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LXT914
Flexible Quad Ethernet Repeater
Datasheet
The LXT914 is an integrated multi-port repeater designed for mixed-media networks. It provides all the active circuitry required for the repeater function in a single CMOS device. It includes one Attachment Unit Interface (AUI) port and four 10BASE-T transceivers. The AUI port is mode selectable: DTE mode allows connection of an external transceiver (10BASE2, 10BASE5, 10BASE-T or FOIRL) or a drop cable. MAU mode creates a MAU output allowing direct connection to another DTE interface. The 10BASE-T transceivers are entirely selfcontained with internal filters which simplify the design work required for FCC-compliant EMI performance. An inter-repeater backplane interface allows 128 or more 10BASE-T ports to be cascaded together. In addition, a serial port provides information for network management. The LXT914 requires only a single 5-volt power supply due to an advanced CMOS fabrication process.
Product Features
s s s s s s s
Four integrated 10BASE-T transceivers and one AUI transceiver on a single chip Programmable DTE/MAU interface on AUI port Seven integrated LED drivers with four unique operational modes On-chip transmit and receive filtering Automatic partitioning of faulty ports, enabled on an individual port basis Automatic polarity detection and correction Programmable squelch level allows extended range in low-noise environments
s
s
s s s
Synchronous or asynchronous interrepeater backplane supports "hot swapping" Inter-repeater backplane allows cascaded repeaters, linking 128 or more 10BASE-T ports Serial port for selecting programmable options 68-pin PLCC (Commercial or Extended temp range) 100-pin PQFP (Commercial temp range)
Applications
s s
LAN Repeaters Integrated Repeaters
s
Switched Repeater Clusters
As of January 15, 2001, this document replaces the Level One document known as Flexible Quad Ethernet Repeater.
Order Number: 248989-001 January 2001
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT914 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners.
Datasheet
Flexible Quad Ethernet Repeater -- LXT914
Contents
1.0 2.0 LXT914 Pin Assignments and Signal Descriptions ..................................... 7 Functional Description...........................................................................................14
2.1 2.2 Introduction..........................................................................................................14 External Interfaces ..............................................................................................14 2.2.1 10BASE-T Ports .....................................................................................14 2.2.2 AUI Port..................................................................................................14 2.2.3 Serial Port...............................................................................................15 2.2.4 Inter-Repeater Backplane ......................................................................15 2.2.4.1 Synchronous IRB Operation......................................................15 2.2.4.2 Asynchronous IRB Operation ....................................................15 Internal Repeater Circuitry ..................................................................................16 Initialization..........................................................................................................16 2.4.1 Local Management Mode Initialization ...................................................16 2.4.2 External Management Mode Initialization ..............................................20 10BASE-T Port Operation ...................................................................................21 2.5.1 10BASE-T Reception .............................................................................21 2.5.1.1 Programmable Internal Squelch Level ......................................22 2.5.1.2 Polarity Detection and Correction..............................................22 2.5.2 10BASE-T Transmission ........................................................................22 2.5.3 10BASE-T Link Integrity Testing ............................................................22 AUI Port Operation ..............................................................................................23 2.6.1 AUI Reception ........................................................................................23 2.6.2 AUI Transmission ...................................................................................23 2.6.3 AUI Mode Selection (DTE/MAU) ............................................................23 Collision Handling................................................................................................24 Security Mode .....................................................................................................24 LED Display.........................................................................................................25 12-Port Hub Repeater .........................................................................................28 8-Port Print or File Server....................................................................................28
2.3 2.4
2.5
2.6
2.7 2.8 2.9
3.0
Application Information.........................................................................................28
3.1 3.2
4.0 5.0
Test Specifications ..................................................................................................36 Mechanical Specifications....................................................................................41
Datasheet
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LXT914 -- Flexible Quad Ethernet Repeater
Figures
1 2 3 4 5 6 7 8 9 10 11 LXT914 Block Diagram ......................................................................................... 7 LXT914 Pin Assignments...................................................................................... 8 Global State Machine.......................................................................................... 18 Partitioning State Machine .................................................................................. 19 Integrated LED Driver Indications ....................................................................... 27 12-Port Application Schematic, 68-Pin PLCC Package ...................................... 30 8-Port Application Schematic, LED Mode 1 with AUISEL = MAU....................... 34 Serial Port Timing................................................................................................ 39 Inter-Repeater Bus Timing .................................................................................. 40 LXT914PC/PE Package Specifications............................................................... 41 LXT914QC Package Specifications .................................................................... 42
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 LXT914 Power, Ground and Clock Signal Descriptions........................................ 9 LXT914 Inter-Repeater Backplane Signal Descriptions...................................... 10 LXT914 Mode Select and Control Signal Descriptions ....................................... 10 LXT914 Serial Port Signal Descriptions (External Management Mode) ............. 11 LXT914 Serial Port Signal Descriptions (Local Management Mode) .................. 11 LXT914 Miscellaneous Control Signal Descriptions ........................................... 12 LXT914 LED Driver Signal Descriptions ............................................................. 12 LXT914 Repeater Port Signal Descriptions ........................................................ 13 Setup Register Bit Assignments.......................................................................... 20 Setup Register Bit Definitions ............................................................................. 20 Packet Status Register Bit Assignments............................................................. 21 Packet Status Register Bit Definitions................................................................. 21 AUI Mode Selection (DTE/MAU) ......................................................................... 23 LED Mode Selection ........................................................................................... 25 Mode 0 (Default) LED Truth Table ...................................................................... 25 Mode 1 LED Truth Table..................................................................................... 26 Mode 2 LED Truth Table..................................................................................... 26 Mode 3 LED Truth Table..................................................................................... 26 Manufacturers Magnetics List ............................................................................. 29 Absolute Maximum Ratings ................................................................................ 36 Recommended Operating Conditions ................................................................. 36 I/O Electrical Characteristics1 (over recommended range) ................................. 36 AUI Electrical Characteristics (over recommended range) ................................. 37 Twisted-Pair Electrical Characteristics (over recommended range) ................... 37 IRB Electrical Characteristics (over recommended range) ................................. 38 Switching Characteristics (over recommended range) ....................................... 38 Serial Port Timing--External Mode (over recommended range) ........................ 38 Inter-Repeater Bus Timing (over recommended range) ..................................... 39
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Datasheet
Flexible Quad Ethernet Repeater -- LXT914
Revision History
Revision Date Description
Datasheet
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Flexible Quad Ethernet Repeater -- LXT914
1.0
LXT914 Pin Assignments and Signal Descriptions
Figure 1. LXT914 Block Diagram
FPS/SECAUI LOC/EXT A/SYNC DOP DON DIP DIN DO/DI DO/DI DO/DI DOP DON DIP DIN CIP CIN AUISEL* 4 4 4
RESET SYSCLK SENI SENO SDI SDO SCLK IRENA IRDEN IRCFS IRCOL IRDAT BCLKIO 4 LED Drivers TP1 - 4 AUI CF JM
Filter
Twisted-Pair Port #1
Control
Management Port (Serial I/F)
F F F
TP Port #2 TP Port #3 TP Port #4
Repeater (State Machine, Timing Recovery, FIFO, etc.)
Inter-Repeater Backplane Port
AUI Port
(Mode selectable DTE/MAU) * The AUI Select function is provided on a dedicated AUISEL pin in the 100-pin PQFP (LXT914QC). In the 68-pin PLCC (LXT914PC/PE) the AUI Select function is provided through shared usage of the JM LED pin.
Datasheet
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LXT914 -- Flexible Quad Ethernet Repeater
Figure 2. LXT914 Pin Assignments
BCLKIO SYSCLK A/SYNC LOC/EXT CS/SENI SENO SDI LEDMO/SDO/RTS SCLK/SCLKIO TEST RESET DSQE/SECTP1 SECTP2 SECTP3 SECTP4 FPS/SECAUI VCC4
9 8 7 6 5 4 3 2 1 68 6766 65 6463 62 61 60 10 59 11 58 12 57 13 56 14 55 15 54 16 53 17 Rev # 52 18 51 19 50 20 Part # LXT914PC/PE XX 49 21 LOT # XXXXXX 48 22 FPO # XXXXXXXX 47 23 46 24 45 25 44 26 27 2829 303132 33343536 3738 39 4041 42 43
GND1 IRCOL IRCFS IRDEN IRDAT IRENA VCC3 VCC2 VCC1 VCC8 VCC7 TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3
LXT914PC/PE
TPDIP4 TPDIN4 GND8 TPDON1 TPDOP1 VCC6 TPDOP2 TPDON2 GND7 TPDON3 TPDOP3 VCC5 TPDOP4 TPDON4 GND6 AUICIN AUICIP
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
FPS/SECAUI SECTP4 SECTP3 LEDCF SECTP2 LEDJM/AUISEL SECTP1/DSQE LEDTP1 n/c LEDTP2 RESET LEDTP3 TEST n/c LEDTP4 SCLK/SCLKIO LEDAUI n/c GND2 RTS/SDO/LEDMO LEDM1 SDI GND3 SENO RBIAS SENI/CS GND4 n/c GND5 LOC/EXT A/SYNC AUIDOP n/c AUIDON SYSCLK AUIDIP n/c AUIDIN BCLKIO n/c n/c n/c 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
n/c LEDCF LEDJM/AUISEL LEDTP1 LEDTP2 LEDTP3 LEDTP4 LEDAUI GND1 LEDM1 GND2 RBIAS GND3 GND4 n/c AUIDOP AUIDON AUIDIP AUIDIN n/c
AUISEL n/c n/c VCC1 n/c
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
LXT914QC
Part # LOT # FPO #
LXT914QC XX XXXXXX XXXXXXXX
Rev #
n/c GND9 IRCOL IRCFS IRDEN IRDAT IRENA VCC10 n/c VCC9 VCC8 VCC7 VCC6 TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 n/c
n/c n/c n/c AUICIP AUICIN n/c
n/c GND5 TPDON4 TPDOP4 VCC2 VCC3 TPDOP3 TPDON3 GND6 GND7 TPDON2 TPDOP2 VCC4 VCC5 TPDOP1 TPDON1 GND8
8
n/c n/c TPDIN4 TPDIP4 n/c n/c n/c
Datasheet
Flexible Quad Ethernet Repeater -- LXT914
Table 1.
LXT914 Power, Ground and Clock Signal Descriptions
Pin # Symbol PLCC 1 2 3 26 49 55 67 68 -- -- 9 34 36 38 39 46 52 58 -- 37 PQFP 27 61 62 69 70 88 89 90 91 93 39 41 43 44 58 65 66 73 99 42 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 RBIAS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bias. This pin provides bias current for the internal circuitry. The 100 A bias current is provided through an external 12.4 k resistor to ground. Backplane Clock. This 10 MHz clock synchronizes multiple repeaters on a common backplane. In the synchronous mode, BCLKIO must be supplied to all repeaters from a common external source. In the asynchronous mode, BCLKIO is supplied only when a repeater is outputting data to the bus. Each repeater outputs its internally recovered clock when it takes control of the bus. Other repeaters on the backplane then sync to BCLKIO for the duration of the transmission. System Clock. The required 20 MHz system clock is input at this pin. Clock must have a 40-60 duty cycle with < 10 ns rise time. Ground. These pins provide ground return paths for the various power supply pins. Power Supply Inputs. These pins each require a +5 VDC power supply. The various pins may be supplied from a single power source, but special de-coupling requirements may apply. Each VCC input must be within 0.3 V of every other VCC input. I/O Description
10
4
BCLKIO
I/O
11
6
SYSCLK
I
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LXT914 -- Flexible Quad Ethernet Repeater
Table 2.
LXT914 Inter-Repeater Backplane Signal Descriptions
PLCC 4 PQFP 94 Symbol IRENA I/O I/O Description Inter-Repeater Backplane Enable. This pin allows individual LXT914 repeaters to take control of the Inter-Repeater Backplane (IRB) data bus (IRDAT). The IRENA bus must be pulled up locally by a 330 resistor.1 IRB Data. This pin is used to pass data between multiple repeaters on the IRB. The IRDAT bus must be pulled up locally by a 330 resistor.1 IRB Driver Enable. The IRDEN pin is used to enable external bus drivers which may be required in synchronous systems with large backplanes. This is an active Low signal, maintained for the duration of the data transmission. IRDEN must be pulled up locally by a 330 resistor. IRB Collision Flag Sense (IRCFS) and IRB Collision (IRCOL). These two pins are used for collision signalling between multiple LXT914 devices on the Inter-Repeater Backplane (IRB). Both the IRCFS bus and the IRCOL bus must be pulled up globally with 330 resistors. (IRCFS requires a precision resistor [1%].)2
5
95
IRDAT
I/O
6
96
IRDEN
O
7 8
97 98
IRCFS IRCOL
I/O I/O
NOTES: 1. IRENA and IRDAT can be buffered between boards in multi-board configurations. Where buffering is used, a 330 pull-up resistor can be used on each signal, on each board. Where no buffering is used, the total impedance should be no less than 330 . 2. IRCFS and IRCOL cannot be buffered. In multi-board configurations, the total impedance on IRCOL should be no smaller than 330 . IRCFS should be pulled up only once, by a single 330 , 1% resistor.
Table 3.
LXT914 Mode Select and Control Signal Descriptions
PLCC PQFP Symbol I/O Description Backplane Sync Mode Select. This pin selects the backplane sync mode. When this pin is left floating an internal pull-up defaults to the Asynchronous mode (A/SYNC High). In the asynchronous mode 12 or more LXT914s can be connected on the backplane, and an external 10 MHz backplane clock source is not required. When the synchronous mode is selected (A/SYNC tied Low), 32 or more LXT914s can be connected to the backplane and an external 10 MHz backplane clock source is required. Management Mode Select. This pin selects the management mode. When this pin is left floating, an internal pull-up defaults to the Local management mode (LOC/EXT High). In the Local mode, setup parameters are downloaded from an EEPROM during initialization. Once initialized with the setup parameters, the repeater functions independently. LED Driver or DTE/MAU Select. At reset, this pin selects the mode of the AUI port. If left floating, an internal pull-down device forces the AUI port to DTE mode. If pulled High with an external resistor, the port changes to a MAU, in which case the functions of the LEDJM pin are disabled and the default LED mode (Refer to Table 7) is not available. DTE/MAU Select. This pin changes the mode of the AUI port independent of the condition at reset. This function is available only in the 100-pin PQFP package. LED Mode 0 & 1 Select. These two pins select one of four possible LED modes of operation. The Functional Description section describes the four modes.
12
8
A/SYNC
I
13
9
LOC/EXT
I
28
33
LEDJM/ AUISEL
I/O
-- 17 35
30 14 40
AUISEL
I
LEDM0 LEDM1
I/O I/O
10
Datasheet
Flexible Quad Ethernet Repeater -- LXT914
Table 4.
LXT914 Serial Port Signal Descriptions (External Management Mode)
PLCC PQFP Symbol I/O Description Serial Enable Input. This active Low input is used to access the LXT914 serial interface. To write to the serial input (SDI), an External Management Device (EMD) must drive this pin from High to Low. The input must be asserted Low concurrent with the appearance of data on SDI and remain Low for the duration of the serial input transaction. Serial Enable Output. This active Low output is used to access the serial interface of an EMD. When the LXT914 sends a data stream to the EMD through the serial port (SDO), this output transitions from High to Low and remains Low for the duration of the serial transmission. Serial Data Input. This pin is the input for the EMD serial interface. Setup and operating parameters are supplied to the LXT914 in a serial data stream through this port when operating in the External Management Mode. Serial Data Output. After each packet transmission or interrupt event, the LXT914 reports status information to the EMD in a serial data stream through this port. Serial Clock. This 10 MHz clock synchronizes the serial interface between the LXT914 and the EMD. Both devices must be supplied from the same clock source. In synchronous mode, SCLK and BCLK may be tied together.
14
11
SENI
I
15
12
SENO
O
16
13
SDI
I
17
14
SDO
I/O
18
16
SCLK
I
Table 5.
LXT914 Serial Port Signal Descriptions (Local Management Mode)
PLCC PQFP Symbol I/O Description Chip Select. The LXT914 is designed for use with an EEPROM or similar device which may be used to store setup parameters and serially download them to the LXT914 during initialization. In a single-device application or in the first device of a daisy chain application, this pin is an active High Chip Select output used to enable the EEPROM. Serial Enable Input. In subsequent devices of a daisy-chain configuration, a High-to-Low transition on this pin enables the serial input port (SDI). The input must be asserted concurrent with the appearance of data on SDI and remain Low for the duration of the serial input transaction. Serial Enable Output. During initialization, the LXT914 accepts 48 bits of setup data through the SDI port. After the 48th bit, the LXT914 asserts this pin Low. When multiple LXT914 devices are connected in a daisy-chain, this output is tied to the SENI input of the next device in the chain. Thus each device in the chain is serially enabled by the previous device until all the devices have read in their 48 bits of setup data. Setup Data Input. This pin is the serial input port for the setup parameters (48 bits).This pin should be tied Low if no EEPROM is present. Request To Send. In a single-device application or in the first device of a daisy chain application, this pin outputs a 9-bit, active High sequence. This pin must be tied to the EEPROM DI input to trigger the EEPROM to download its stored data. In subsequent devices this pin is not used. Serial Clock. A 1 MHz clock provided by the first LXT914 in the chain to all subsequent repeaters and the EEPROM. In the Local mode all repeaters have their SCLKIO pins tied together.
CS 14 11 SENI
O
I
15
12
SENO
O
16
13
SDI
I
17
14
RTS
I/O
18
16
SCLKIO
I/O
Datasheet
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LXT914 -- Flexible Quad Ethernet Repeater
Table 6.
LXT914 Miscellaneous Control Signal Descriptions
PLCC 19 20 PQFP 18 19 Symbol TEST RESET DSQE (Local) 21 21 SECTP1 (External) 22 23 24 SECTP2 SECTP3 SECTP4 (External) I I/O I I I Description Test Mode Select. This pin must be tied Low for normal operation. RESET. This pin resets the LXT914 circuitry when pulled High for 1 ms. DSQE. In Local Mode, this pin controls the SQE function. When High, the SQE function of the AUI port is disabled. When Low, SQE is enabled. Security Mode Select (TP Port 1). In External Mode, this pin enables the security mode for twisted-pair port 1. When pulled High, the LXT914 Jams the port. This pin must be tied Low if external security control is not required. Security Mode Select (TP Ports 2-4). In External Mode, these pins enable the security mode for the respective twisted-pair ports (TP1 through TP4). When pulled High, the LXT914 jams the affected port. The SEC pins must be tied Low if external security control is not required. First Position Select. In the Local mode this pin identifies the first device in a daisy chain configuration. When tied High (First position), the LXT914 controls the local EEPROM by providing clock and handshaking. When tied Low (Not First), the LXT914 will accept CLK and data in its turn from previous LXT914s in the data chain. Security Mode Select (AUI Port). In the External mode this pin enables the security mode for the AUI port. When pulled High, the LXT914 jams the AUI port. The security feature is available only in External management mode.
22 23 24
I I I
FPS (Local) 25 25 SECAUI (External)
I
I
Table 7.
LXT914 LED Driver Signal Descriptions
PLCC PQFP Symbol I/O Description Collision & FIFO Error LED Driver. This tri-state LED driver pin reports collisions and FIFO errors. It pulses Low to report collisions, and pulses High to report FIFO errors. When this pin is connected to the anode of one LED and to the cathode of a second LED, the LXT914 will simultaneously monitor and report both conditions independently. Jabber/MJLP & Manchester Code Violation LED Driver. This tri-state LED driver pin reports jabber and code violations. It pulses Low to report MAU Jabber Lockup Protection (MJLP), and pulses High to report Manchester code violations. When this pin is connected to the anode of one LED and to the cathode of a second LED, the LXT914 will simultaneously monitor and report both conditions independently. Twisted-Pair Port LED Drivers. These tri-state LED drivers use an alternating pulsed output to report TP port status. Each pin should be tied to a pair of LEDs (to the anode of one LED and the cathode of a second LED). When connected this way, each pin reports five separate conditions (receive, transmit, link integrity, reverse polarity and auto partition). AUI Port LED Driver. This tri-state LED driver uses an alternating pulsed output to report AUI port status. This pin should be tied to a pair of LEDs (to the anode of one LED and the cathode of a second LED). When connected this way, this pin reports five separate conditions (receive, transmit, receive jabber, receive collision and auto partition.
27
32
LEDCF
O
28
33
LEDJM
O
29 30 31 32
34 35 36 37
LEDTP1 LEDTP2 LEDTP3 LEDTP4
O O O O
33
38
LEDAUI
O
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Datasheet
Flexible Quad Ethernet Repeater -- LXT914
Table 8.
LXT914 Repeater Port Signal Descriptions
PLCC 40 41 42 43 44 45 56 57 54 53 50 51 48 47 66 65 64 63 62 61 60 59 PQFP 46 47 48 49 54 55 71 72 68 67 63 64 60 59 87 86 85 84 83 82 77 76 Symbol AUIDOP AUIDON AUIDIP AUIDIN AUICIP AUICIN TPDOP1 TPDON1 TPDOP2 TPDON2 TPDOP3 TPDON3 TPDOP4 TPDON4 TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 TPDIP4 TPDIN4 I/O O O I I I/O I/O O O O O O O O O I I I I I I I I Twisted-Pair Data Inputs (Positive and Negative). These pins are the positive (TPDIP1-4) and negative (TPDIN1-4) inputs from the network to the respective twisted-pair ports. Twisted-Pair Data Outputs (Positive and Negative). These pins are the positive (TPDOP1-4) and negative (TPDON1-4) outputs to the network from the respective twisted-pair ports. Description AUI Data Outputs (Positive and Negative). These pins are the positive and negative data outputs for the AUI Port. In MAU Mode these pins are connected to the DI pins of the DTE. AUI Data Input (Positive and Negative). These pins are the positive and negative data inputs for the AUI Port. In MAU Mode, these pins are connected to the DO pins of the DTE. AUI Collision (Positive and Negative). These pins are the positive and negative Collision inputs for the AUI Port in DTE Mode. In MAU Mode, these pins output a collision indication to the DTE.
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LXT914 -- Flexible Quad Ethernet Repeater
2.0
2.1
Functional Description
Introduction
The LXT914 is an integrated hub repeater for 10BASE-T networks. The hub repeater is the central point for information transfer across the network. The LXT914 offers multiple operating modes to suit a broad range of applications ranging from simple 4-port stand-alone hubs or attachments for print and file servers, up to intelligent 128-port enterprise systems with microprocessor/gate array management. The main functions of the LXT914 hub repeater are data recovery and re-transmission and collision propagation. Data packets received at the AUI or 10BASE-T ports are detected and recovered by the port receivers before being passed to the repeater core circuitry for re-timing and re-transmission. Data packets received through the IRB port are essentially passed directly to the core for retransmission. After recovery of a valid data packet, the repeater broadcasts it to all enabled stations, except the originator station.
2.2
External Interfaces
The LXT914 includes four 10BASE-T ports with internal filters. The LXT914 also includes an Attachment Unit Interface (AUI) port, a serial port and an Inter-Repeater Backplane (IRB) port. The serial port allows an external device such as an EEPROM to download setup parameters to the repeater. In more complex designs the serial port can also be used to monitor repeater status. The IRB port enables multiple LXT914 devices to be cascaded, creating a large, multi-port repeater.
2.2.1
10BASE-T Ports
The four 10BASE-T transceiver ports are completely self-contained. Since the transmitters and receivers include the required filtering, only simple, inexpensive transformers are required to complete the 10BASE-T interface. Each individual Twisted-Pair (TP) port is implemented in accordance with the IEEE 802.3 10BASE-T standard.
2.2.2
AUI Port
The AUI port mode is selectable (DTE mode or MAU mode). With DTE mode selected, the AUI port allows connection of an external transceiver (10BASE2, 10BASE5, 10BASE-T or FOIRL) or a drop cable. With MAU mode selected, the AUI port establishes a MAU output allowing direct connection to another DTE interface.
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Flexible Quad Ethernet Repeater -- LXT914
2.2.3
Serial Port
The serial port provides the management interface to the LXT914. Refer to Test Specifications for serial port timing. The serial port can be either unidirectional or bidirectional, depending on the management mode selected. In the Local management mode the serial port is unidirectional (input only), and is used only to download setup parameters during initialization. The Local mode is intended for use with a simple EEPROM, but the serial port may be tied Low if an EEPROM is not required. In the External management mode, the serial port is bi-directional (input for setup parameters, output for status reports). The External mode is intended for use with an External Management Device (EMD) and a Media Access Controller (MAC). The EMD (typically a gate array) communicates with a microprocessor (e.g., Intel 8051) and can control up to three LXT914 repeaters. This simplifies design of a relatively standard 12-port repeater on a single printed circuit board.
2.2.4
Inter-Repeater Backplane
The Inter-Repeater Backplane (IRB) allows several LXT914s to function as a single repeater. Refer to Test Specifications for IRB timing. The IRB also allows several multi-repeater boards to be integrated in a standard rack and to function as a single unit. The IRB supports "hot swapping" for easy maintenance and troubleshooting. Each individual repeater distributes recovered and re-timed data to other repeaters on the IRB for broadcast on all ports simultaneously. This simultaneous rebroadcast allows the multi-repeater system to act as a single large repeater unit. The maximum number of repeaters on the IRB is limited by bus loading factors such as parasitic capacitance. The IRB can be operated synchronously or asynchronously.
2.2.4.1
Synchronous IRB Operation
In the synchronous mode, a common external source provides the 10 MHz backplane clock (BCLKIO) and the 20 MHz system clock (SYSCLK) to all repeaters. BCLKIO must be synchronous to SYSCLK and may be derived from SYSCLK using a divide-by-two circuit. In the synchronous mode 32 or more LXT914 repeaters may be connected on the IRB, providing 128 10BASE-T ports and 32 AUI ports.
2.2.4.2
Asynchronous IRB Operation
In the asynchronous mode an external BCLKIO source is not required. The repeaters run independently until one takes control of the IRB. The transmitting repeater then outputs its own 10 MHz clock onto the BCLKIO line. All other repeaters sync to that clock for the duration of the transmission. In the asynchronous mode 12 or more LXT914 devices may be connected to the IRB, providing 48 10BASE-T ports and 12 AUI ports.
Note:
The maximum number of repeaters which may be linked on the backplane is limited by board design factors. The numbers listed above are engineering estimates only. Stronger drivers and reduced capacitive loading in PCB layout may allow an increased device count.
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LXT914 -- Flexible Quad Ethernet Repeater
2.3
Internal Repeater Circuitry
The basic repeater circuitry is shared among all the ports within the LXT914. It consists of a global repeater state machine, several timers and counters and the timing recovery circuit. The timing recovery circuit includes a FIFO for re-timing and recovery of the clock which is used to clock the receive data out onto the IRB. The shared functional blocks of the LXT914 are controlled by the global state machine (Figure 3). This diagram and all associated notations used are in strict accordance with section 9.6 of the IEEE 802.3 standard. The LXT914 also implements the Partition State Diagram as defined by the IEEE 802.3 standard and shown in Figure 4. The value of CCLimit as implemented in the LXT914 is 64. The CCLimit value sets the number of consecutive collisions that must occur before the port is subjected to automatic partitioning. Auto-partition/re-connection is also supported by the LXT914 with Tw5 conforming to the standard requirement of 450 to 560 bit times.
2.4
Initialization
The following description applies to the initial power-on reset and to any subsequent hardware reset. When a reset occurs (RESET pin pulled High for > 1 ms), the device senses the levels at the various control pins (see Table 3) to determine the correct operating modes for Management, LEDs, and the AUI port functions.
2.4.1
Local Management Mode Initialization
An internal pull-up causes the LXT914 to default to the Local management mode unless the LOC/ EXT pin is tied Low. In the Local mode the serial port is a unidirectional interface used only to download setup parameters from an external device. In a Locally managed multiple-repeater (daisy chain) configuration, the first repeater in the chain performs special functions. The First Position Select (FPS) pin is used to establish position (FPS High = First, FPS Low = Not First). After establishing the Hardware mode, each LXT914 monitors the FPS pin to determine its position. If FPS is High (First Position), the repeater performs the following functions: 1. Outputs a 1 MHz Serial Clock (SCLK). SCLK is derived from the 20 MHz SYSCLK input in ASYNC mode and from BCLKIO in SYNC mode; it is supplied to the SCLK inputs of all other repeaters on the bus and to the EEPROM. 2. Asserts Chip Select (CS) High to enable the EEPROM. 3. Outputs a serial 9-bit request-to-send (RTS) strobe. The programmable device responds to the RTS strobe with a serial data stream containing the setup parameters for all repeaters in the chain. 4. Clocks the first 48 serial data input (SDI) bits from the EEPROM into its setup register. Refer to Table 9 and Table 10 for Setup Register bit assignments. 5. Asserts Serial Enable Output (SENO) Low to enable the next repeater in line.
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Datasheet
Flexible Quad Ethernet Repeater -- LXT914
The second repeater has FPS tied Low and Serial Enable Input (SENI) connected to the Serial Enable Output (SENO) of the first repeater. When enabled by a Low on SENI, each repeater downloads its portion of the stream, then stops accepting data and asserts SENO Low. The SENO pin is linked to the SENI input of the next repeater. This enables the next repeater to clock in its 48bit word and so on. If FPS is Low (Not First Position), the repeater performs the following functions: 1. Syncs to the 1 MHz Serial Clock (SCLK) input. SCLK is supplied by the First Position repeater. 2. Responds to SENI Low by enabling the SDI port. 3. Clocks 48 bits from the EEPROM into its setup register through the SDI port. 4. Asserts SENO Low to enable the next repeater in line.
Datasheet
17
LXT914 -- Flexible Quad Ethernet Repeater
Figure 3. Global State Machine
Power On
START Begin UCT IDLE Out (ALL) = Idle
Collin(ANY) = SQE[NA Port(Collin = SQE)] Datain(ANY) = II * Collin(ALL) = SQE:[N Port(Datain = II)] A
SEND PREAMBLE PATTERN Out (ALLXN) = Preamble Pattern
Collin(ANYXN) = SQE Collin(N) = SQE + Datain(N) = II * Collin (ALL) = SQE TT(ALLXN) 62 * DataRdy * Collin(ALL) = SQE * Datain(N) = II
SEND TWO ONES Out (ALLXN) = TwoOnes
Collin(ANYXN) = SQE Collin(N) = SQE + Datain = II * Collin(ALL) = SQE TwoOnesSent * Collin(ALL) = SQE * Datain(N) = II
SEND DATA Out (ALLXN) = Data
Collin(ANYXN) = SQE Collin(N) = SQE + Datain(N) = II * Collin(ALL) = SQE * AllDataSent * TT(ANAYXN) < 96
TRANSMIT COLLISION Out (All) = Jam
Collin(ANYXN) = SQE Collin(ALL) = SQE * TT(ALL) 96 * Tw2Done Collin(ONLY1) = SQE * TT(ALL) 96:[MA Port(Collin = SQE)] Datain(N) = II * Collin(ALL) = SQE * TT(ALLXN) 96 * AllDataSent
RECEIVE COLLISION Out (ALLXN) = Jam
Datain(N) = II * Collin(ALL) = SQE * TT(ALLXN) 96 * Tw2Done
ONE PORT LEFT Out (ALLXM) = Jam
Collin(ANYXM) = SQE Datain(M) = II* Collin(ALL) = SQE* Tw2Done
WAIT StartTw1 Out(ALL) = Idle
Collin(ANY) = SQE + Tw1Done
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Datasheet
Flexible Quad Ethernet Repeater -- LXT914
Figure 4. Partitioning State Machine
Begin
COUNT CLEAR CC(X) = 0 Datain(X) = DIPresent(X) Collin(X) = CIPresent(X) DIPresent(X) = II * CIPresent(X) = SQE
COLLISION COUNT IDLE Datain(X) = DIPresent(X) Collin(X) = CIPresent(X)
PARTITION WAIT Datain(X) = II Collin(X) = SQE
DIPresent(X) = II + CIPresent(X) = SQE
DIPresent(X) = II *CIPresent(X) = SQE
WATCH FOR COLLISION StartTw5 Datain(X) = DIPresent(X) Collin(X) = CIPresent(X)
PARTITION HOLD Datain(X) = II Collin(X) = SQE
DIPresent(X) = II * CIPresent(X) = SQE Tw5Done * DIPresent(X) = II * CIPresent(X) = SQE CIPresent(X) = SQE
DIPresent(X) = II + CIPresent(X) = SQE COLLSION COUNT INCREMENT CC(X) = CC(X) + 1 Datain(X) = DIPresent(X) Collin(X) = CIPresent(X) StartTw6 CC(X) CCLimit + (Tw6Done * CIPresent(X) = SQE) DIPresent(X) = II * CIPresent(X) = SQE * CC(X) < CCLimit * Tw6Done
PARTITION COLLISION WATCH Datain(X) = II Collin(X) = SQE StartTw5
CIPresent(X) = SQE
DIPresent(X) = II CIPresent = SQE
Tw5Done * DIPresent(X) = II * CIPresent(X) = SQE
WAIT TO RESTORE PORT Datain(X) = II Collin(X) = SQE CC(X) = 0 DIPresent(X) = II * CIPresent (X) = SQE
Datasheet
19
LXT914 -- Flexible Quad Ethernet Repeater
Table 9.
Setup Register Bit Assignments
Register SR(0) SR(1) SR(2) SR(3) SR(4) SR(5) D7 DISLI3 DISTX2 ERSQ1 DFIFOE RES RES D6 DISLI2 DISTX1 DISRX4 DPFRM RES RES D5 DISLI1 DISTXA DISRX3 DSQE RES RES D4 DISAP4 DPRC4 DISRX2 DMCV RES RES D3 DISAP3 DPRC3 DISRX1 ERXJAB RES RES D2 DISAP2 DPRC2 DISRXA ERSQ4 RES RES D1 DISAP1 DPRC1 DISTX4 ERSQ3 RES RES D0 DISAPA DISLI4 DISTX3 ERSQ2 RES RES
Table 10. Setup Register Bit Definitions
Bit DISAPx DISLIx DPRCx DISTXx DISRXx ERSQx ERXJAB DMCV DSQE DPFRM DFIFOE DMJLP RES 1 = Disable Auto-Partitioning on Port x 1 = Disable Link Integrity on Port x (Twisted-pair ports only) 1 = Disable Polarity Reverse detection and Correction on Port x (Twisted-pair ports only) 1 = Disable Transmit on Port x 1 = Disable Receive on Port x 1 = Enable Reduced Squelch on Port x (Twisted-pair ports only) 1 = Enable Receive JAB (Long Packet) (Global) 1 = Disable entering Tx Collision state on reception of Manchester Code Violation 1 = Disable Signal Quality Error to provide heartbeat (AUI port only) 1 = Disable End-of-Frame checking for polarity correction (Global) 1 = Disable entering Tx Collision state on FIFO over/underflow condition (Global) 1 = Disable MJLP counter (Global) Reserved. Must be set to 0. Definition
2.4.2
External Management Mode Initialization
The LXT914 operates in the External management mode when the LOC/EXT pin is tied Low. In the External mode, the serial port is a bidirectional interface between the LXT914 and an external management device (EMD). The serial port is used to download initial setup parameters to the repeater and to monitor status reports from the repeater. The LXT914 setup parameters can be changed at any time by the EMD. The initialization process for each repeater in a managed mode configuration is the same, regardless of its position; each repeater is connected directly to the EMD. Each LXT914 initializes as follows: 1. Syncs to the 10 MHz Serial Clock (SCLK) input. SCLK must be supplied from an external source. 2. Responds to SENI Low by enabling the SDI port. 3. Clocks 48 bits from the EMD into its setup register through the SDI port. 4. Once initialized, the LXT914 reports its status in a 48-bit serial stream after every packet transmission or interrupt event. Refer to Table 11 and Table 12 for packet status register bit assignments and definitions.
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Datasheet
Flexible Quad Ethernet Repeater -- LXT914
Table 11. Packet Status Register Bit Assignments
Register PSR(0) PSR(1) PSR(2) PSR(3) PSR(4) PSR(5) D7 COL2 PR2 SPA LP3 RXJABA RES D6 COL1 PR1 AP4 LP2 MJLP RXCOL D5 COLA LLS4 AP3 LP1 LCOL4 MANCV D4 RX4 LLS3 AP2 LPA LCOL3 FIFOER D3 RX3 LLS2 AP1 SP4 LCOL2 RXJAB4 D2 RX2 LLS1 APA SP3 LCOL1 RXJAB3 D1 RX1 COL4 PR4 SP2 LCOLA RXJAB2 D0 RXA COL3 PR3 SP1 LP4 RXJAB1
Table 12. Packet Status Register Bit Definitions
Bit RXx COLx LLSCx PRx APx SPx LPx LCOLx MJLP RXJABx FIFOER MANCV RXCOL RES Definition Received Packet on Twisted-Pair Port 1-4 or on AUI Port Transmit Collision of Twisted -Pair Port 1-4 or on AUI Port Link Loss State on Twisted-Pair Port 1-4 or on AUI Port Polarity reversed on Twisted-Pair Port 1-4 or on AUI Port Auto-Partition circuit isolated Twisted-Pair Port 1-4 or the AUI Port Short Packet (less than 74 bits) on Twisted-Pair Port 1-4 or on AUI Port Long Packet (more than 1.3 ms) on Twisted-Pair Port 1-4 or on AUI Port Late Collision on Twisted-Pair Port 1-4 or on AUI Port MAU Jabber Lockup Protection Receive Jabber Lockup Protection FIFO overflow/underflow Manchester Code Violation Receive Collision on the AUI Port Reserved. Not used
The notation ABCDx means bit ABCD associated with port x, which can be any of the four Twisted-Pair Ports or the AUI Port.
2.5
2.5.1
10BASE-T Port Operation
10BASE-T Reception
Each LXT914 10BASE-T port receiver acquires data packets from its twisted-pair input (TPDIP/ TPDIN). An internal RC filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. The receive function is activated only by valid data streams (above the squelch level and with proper timing). If the differential signal at the DI circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical), the port receiver enters the idle state.
Datasheet
21
LXT914 -- Flexible Quad Ethernet Repeater
2.5.1.1
Programmable Internal Squelch Level
The 10BASE-T port receivers have two squelch levels: a normal level or default setting and a reduced level squelch (-4.5 dB) selected when the ERSQx is set in the Setup register. When used with Low noise media such as shielded twisted-pair cabling, the reduced squelch level allows longer loop lengths in the network.
2.5.1.2
Polarity Detection and Correction
The LXT914 10BASE-T ports detect and correct for reversed polarity by monitoring link pulses and end-of-frame sequences. A reversed polarity condition is declared when the port receives sixteen or more incorrect link pulses consecutively, or four frames with reversed start-of-idle sequence. In these cases the receiver reverses the polarity of the signal and thereby corrects for this failure condition. If the port enters the link fail state and no valid data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. (If Link Integrity Testing is disabled, polarity detection is based only on received data.)
2.5.2
10BASE-T Transmission
Each LXT914 10BASE-T port receives NRZ data from the repeater core and passes it through a Manchester encoder. The encoded data is then transmitted to the twisted-pair network (the DO circuit). The advanced integrated pulse shaping and filtering network produces the pre-distorted and pre-filtered output signal to meet the 10BASE-T jitter template. An internal continuous resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse shaping circuitry. Integrated filters simplify the design work required for FCC compliant EMI performance. During idle periods, the LXT914 10BASE-T ports transmit link integrity test pulses in accordance with the 802.3 10BASE-T standard. Data packets transmitted by the LXT914 contain a minimum of 56 preamble bits before the start of frame delimiter (SFD). In the Asynchronous mode, preamble regeneration takes place on the transmit side. In the Synchronous mode, the preamble is regenerated on the receive side and distributed via the IRB. If the total packet is less than 96 bits including the preamble, the LXT914 extends the packet length to 96 bits by appending a Jam signal (1010...) at the end.
2.5.3
10BASE-T Link Integrity Testing
The LXT914 fully supports the 10BASE-T Link Integrity test function. The link integrity test determines the status of the receive side twisted-pair cable. Link integrity testing is enabled unless disabled via the DISLIx bit in the Setup register. When enabled, the receiver recognizes link integrity pulses transmitted in the absence of data traffic. With no data packets or link integrity pulses within 100 (50) ms, the port enters a link fail state and disables its transmitter. The port remains in the link fail state until it detects three or more data packets or link integrity pulses.
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Datasheet
Flexible Quad Ethernet Repeater -- LXT914
2.6
2.6.1
AUI Port Operation
AUI Reception
The LXT914 AUI port receiver acquires data packets from the network (AUIDIP/AUIDIN). Only valid data streams above the squelch level activate the receive function. If the differential signal at the DI circuit inputs falls below 75% of the threshold level (unsquelched) for 8 bit times (typical), the AUI receiver enters the idle state.
2.6.2
AUI Transmission
The LXT914 AUI port receives NRZ data from the repeater core, and passes it through a Manchester encoder. The encoded data then goes out on the network (AUIDOP/AUIDON).
2.6.3
AUI Mode Selection (DTE/MAU)
The LXT914 allows the user to change the mode of the AUI from a DTE to a MAU interface. This option is available on both 68- and 100-pin versions except as follows:
* When using the LEDJM/AUISEL pin to select the AUI interface mode the following is true:
After reset the state of the LEDJM/AUISEL pin is sensed for the correct mode. The LEDJM/ AUISEL pin when floated or pulled Low will select the DTE interface and the LEDJM/ AUISEL output is still available. When the LEDJM/AUISEL pin is pulled High the MAU interface is selected and the LEDJM/AUISEL function is unavailable.
* The 100-pin PQFP has an additional pin, AUISEL (pin 30). When using this pin to select the
AUI interface mode the LEDJM/AUISEL pin is still a functional LED driver. The AUISEL pin is not latched after reset and is actively polled to determine which AUI interface mode is to be used. Refer to Table 13. Table 13. AUI Mode Selection (DTE/MAU)
App # 1 2 3 4 AUISEL (PQFP only) Low Low High High LEDJM/ AUISEL (both pkgs) Low High Low High AUI Mode DTE MAU MAU MAU Available LED Modes default, 0-3 1-3 default, 0-3 1-3
Application 3 is valid only when using the 100-pin PQFP.
Datasheet
23
LXT914 -- Flexible Quad Ethernet Repeater
2.7
Collision Handling
A collision occurs when two or more repeater ports receive simultaneously, or when the AUI CIP/ CIN signal is active. The LXT914 fully complies with the IEEE 802.3 collision specifications, both in individual and multi-repeater applications. In multiple-repeater configurations, collision signaling on the IRB allows all repeaters to share collision parameters, acting as a single large repeater. IRCOL is a digital open-drain pin. IRCFS is an analog/digital port. The IRCOL and IRCFS lines are pulled up globally (i.e., each signal requires one pull-up resistor for all boards). If there are eight 3-repeater boards in the system, all eight boards share a single pull-up resistor for IRCOL and a single pull-up resistor for IRCFS. The global pull-up may be located on one of the boards, or on the backplane. The IRCFS line requires a precision ( 1%) resistor. The IRENA, IRDAT and IRDEN lines are each pulled up locally (one pull-up resistor per board) if external bus drivers are used. If no bus drivers are used then only one global pull-up per signal is used.
2.8
Security Mode
The LXT914 security mode is fully transparent to the user. In the External management mode, the security feature is available for all four TP ports and the AUI port. In the Local mode, security is available for the TP ports only (the SECAUI input is reassigned as FPS). The security inputs are normally held Low to disable the security feature. Any input can independently be pulled High to scramble the respective port for any given length of time. For applications which do not require security control, the SEC pins must be tied Low. The security mode pins are real time response inputs. This allows the board designer to screen the destination address with an application specific device and (on match of the destination address) to assert the security input to jam the respective port for the given frame. This real time detection and jam assertion method provides the flexibility to implement customer specific solutions. The destination address decoding and security signal assertion functions can be integrated into the external management device.
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Datasheet
Flexible Quad Ethernet Repeater -- LXT914
2.9
LED Display
The LED display interface consists of seven integrated LED drivers, one for each of the five network ports and two for common functions. Each pin provides a three-state pulsed output (+5 V, high Z, and 0 V) which allows multiple conditions to be monitored and reported independently. Table 14 shows the LED Mode selected with each LEDM1 and LEDM0 combination. Figure 5 shows the LED Driver output conditions, and Tables 15 through 18 list the repeater states associated with each of the five conditions. Note: If LED mode 0 is selected and the LEDJM/AUISEL pin is High (which selects MAU Mode), the device defaults to LED Mode 1. LED Mode 0 is not available when LEDJM/AUISEL is pulled High.
Table 14. LED Mode Selection
LEDM1 PLCC pin PQFP pin 35 40 Low Low High High LEDM0 17 14 Low High Low High 0 (default) 1 2 3 LED Mode Selected
This mode is not available when using the LEDJM/AUISEL pin to select a MAU interface in the AUI port. In this case, the LED Mode defaults to LED Mode 1.
LED Mode 0 (Default)
This mode is selected when LEDM1 and LEDM0 are floating or pulled Low. Refer to Table 15. This mode is not available when using the LEDJM/AUISEL pin to select a MAU interface in the AUI port. In this case, the LED Mode defaults to Mode 1. This mode is selected when LEDM1 is floating or pulled Low and LEDM0 is pulled High by a pull-up resistor. Refer to Table 16. This mode is selected when LEDM1 is pulled High by a pull-up resistor and LEDM0 is floating or pulled Low. Refer to Table 17. This mode is selected when LEDM1 is pulled High by a pull-up resistor and LEDM0 is also pulled High by a pull-up resistor. Refer to Table 18.
LED Mode 1 LED Mode 2 LED Mode 3.
Table 15. Mode 0 (Default) LED Truth Table
Condition 1 2 3 4 5 LEDTP 1-4 Rx Link Pulse Tx Packet Reversed Polarity Rx Packet Partitioned Out LEDAUI N/A Tx Packet N/A Rx Packet Partitioned Out LEDCF FIFO Error N/A Collision N/A N/A LEDJM Manchester Code Violation N/A MAU Jabber Lockup Protection (MJLP) N/A N/A
Datasheet
25
LXT914 -- Flexible Quad Ethernet Repeater
Table 16. Mode 1 LED Truth Table
Condition 1 2 3 4 5 LEDTP 1-4 Rx Link Pulse N/A N/A Rx Packet N/A LEDAUI N/A N/A N/A Rx Packet N/A LEDCF MAU Jabber Lockup Protection (MJLP) N/A Collision N/A N/A LEDJM N/A N/A N/A N/A N/A
Table 17. Mode 2 LED Truth Table
Condition 1 2 3 4 5 LEDTP 1-4 Rx Link Pulse Partitioned Out N/A Rx Packet N/A LEDAUI N/A Partitioned Out N/A Rx Packet N/A LEDCF MAU Jabber Lockup Protection (MJLP) N/A Collision N/A N/A LEDJM N/A N/A N/A N/A N/A
Table 18. Mode 3 LED Truth Table
Condition 1 2 3 4 5 LEDTP 1-4 Rx Link Pulse Rx Packet Partitioned Out N/A N/A LEDAUI N/A Rx Packet Partitioned Out N/A N/A LEDCF MAU Jabber Lockup Protection (MJLP) N/A Collision N/A N/A LEDJM N/A N/A N/A N/A N/A
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Datasheet
Flexible Quad Ethernet Repeater -- LXT914
Figure 5. Integrated LED Driver Indications
2 mA Operation
Red +5 V 820 Red 470 Green
5 mA Operation
LXT914 LED Driver
Green
+5 V 330
LXT914 LED Driver
70
820
330
Condition 1: Steady Green
4 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms
+5V High Z 0V (Gnd)
Condition 2: Blinking Green
4 ms 4 ms 4 ms
256 ms 256 ms 4 ms 4 ms 4 ms 4 ms
+5V High Z 0V (Gnd)
Condition 3: Steady Red
4 ms 4 ms 4 ms 4 ms 4 ms 4 ms
+5V High Z 0V (Gnd)
Condition 4: Blinking Red
4 ms 4 ms 256 ms 4 ms 4 ms
256 ms
4 ms 4 ms
4 ms 4 ms
+5V High Z 0V (Gnd)
Condition 5: Alternating Red/Green
4 ms 4 ms 4 ms
5.33 Hz 4 ms 4 ms 4 ms 4 ms
+5V High Z 0V (Gnd)
93.75 ms
Datasheet
27
LXT914 -- Flexible Quad Ethernet Repeater
3.0
3.1
Application Information
12-Port Hub Repeater
Figure 6 (Sheets 1 through 4) shows a simple 12-port hub repeater application with 3 LXT914s. This application also provides two additional AUI ports--one DB-15 connector and one coaxial port. The application shown uses the asynchronous backplane mode so no external backplane clock source is required. Figure 6 (Sheet 1) shows the XL93C46 EEPROM which downloads the setup parameters for all the LXT914 devices at initialization. (This EEPROM could be replaced with a simple pull down resistor on the SDI pin. This will select the default conditions of the set up register.) A single 20 MHz crystal provides the SYSCLK for all three LXT914 chips. The LXT914 hub repeater on Sheet 1 provides the AUI DB-15 connector as well as four twisted-pair ports. Table 19 lists transformers suggested for use with the LXT914. Figure 6 (Sheet 2) shows a second LXT914 hub repeater with four TP ports and a coaxial port. The MD-001 coax transceiver is used to implement the port. Sheet 3 shows the third LXT914 device with its four TP ports and indicator LEDs. The AUI port of the third LXT914 hub repeater is not used. Sheet 4 of the schematic shows the LEDs for the remaining LXT914 devices, along with the LED operation table.
3.2
8-Port Print or File Server
Figure 7 (Sheets 1 and 2) shows an eight-port repeater attachment for an existing single port AUI or 10BASE5 interface. This application can be added to a current design with an existing AUI or 10BASE5 interface. This circuit allows increased connectivity without the need for another external remote hub. The application shown is a 68-pin PLCC, an asynchronous backplane with both LXT914s in the first position. In Figure 7 (Sheet 1) the LXT914 is set up with the LEDs in Mode 1 with one LED per port and a single collision LED. The twisted pair port LEDs display link integrity only. (Refer to Table 16.) LED Mode 1 is selected by pulling LEDM0 High with a 1 k resistor on pin 17 and pulling LEDM1 Low with pin 35 attached to ground. Figure 7 (Sheet 2) has the same configuration, mode of operation and LED Mode as used in Sheet 1. However, the AUI port has been configured as a MAU interface. This is selected when LEDJM/ AUISEL on pin 28 is pulled up through a 1 k resistor. This mode disables the LEDJM pin as an LED driver. (See Table 13.) The MAU interface now configured on the LXT914 allows the AUI port to attach to a DTE interface. This application increases connectivity to any existing single-port Ethernet design. This unique application allows the designer to integrate an external hub, eliminating the need for additional external equipment.
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Datasheet
Flexible Quad Ethernet Repeater -- LXT914
Table 19. Manufacturers Magnetics List
Manufacturer Bell Fuse Fil-Mag HALO Quad Transmit S553-5999-02 23Z339 TD54-1006L1 TG54-1006N2 (Octal) Kappa Nanopulse PCA Pulse Eng. VALOR TP4003P 5976 EPE6009 PE68810 PT4116 TP497P101 5977 EPE6010 PE68820 PT4117 PE65745; PE65994; PE65746; PE65998 PT4069N1; PT4068N1; ST7011S2; ST7010S2 Quad Receive S553-5999-03 23Z338 TD01-1006L1 TG01-1006N2 TD42-2006Q; TD43-2006K; TG42-1406N1 TG43-1406N TG44-S010NX Tx/Rx Pairs
Datasheet
29
30
CLK10 IRENA IRDAT IRCFS IRCOL U2 SK CS 330 1% 330 330 330 4 DO DI XL93C46 VCC 3 2 1 R18 R17 R19 R16
INSTALL EITHER RESISTOR OR EEPROM
R22
0 Ohm
GND
1
U1
SENO1
SCLKIO
SDIN 12 13 VCC C4 A/SYNC* LOC/EXT* SYSCLK BCLKIO RESET 120pF C3 C6 LEDM1 TEST RBIAS 120pF T2 120pF LEDCF LEDJM/AUISEL 27 28
15 17 18 14 16 SENO* RTS/SDO/LEDM0 SCLKIO CS/SENI* SDI IRENA* IRDAT IRDEN* IRCFS* IRCOL* 4 5 6 7 8
COLLED AUILED TP1LED TP2LED TP3LED TP4LED
Y1 20
11 10
1
NC
CN1D
OUT 35 19 37 12.4K R20 1% LEDAUI LEDTP1 LEDTP2 LEDTP3 LEDTP4
8
20Mhz
CLK20 GND
33 29 30 31 32
1 2 3 4 5 6 7 8 RJ45X4 CN1C
TP1
VCC GND C5 R4 120pF T1 R1 100 1% 100 1%
21 22 23 24 25 SECTP1/DSQE SECTP2 SECTP3 SECTP4 FPS/SECAUI TPDOP1 TPDON1 TPDOP2 TPDON2 TPDOP3 TPDON3 TPDOP4 TPDON4 TX1:1.41X4 R8 R9 R10 R11 R12 R13 R14 R15 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 1% 1% 1% 1% 1% 1% 1% 1%
LXT914 -- Flexible Quad Ethernet Repeater
VCC
56 57 54 53 50 51 48 47
1 2 3 4 5 6 7 8 RJ45X4 CN1B
TP2
C2 .1uF
RESET LXT914PC R2 F1 +12 R7 78.7 1% 0 R6 78.7 1% R5 78.7 1% FUSE C1 33uF 100 1% R3 100 1%
40 41 42 43 44 45 AUIDOP AUIDON AUIDIP AUIDIN AUICIP AUICIN 1 2 3 4 5 6 7 8
TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 TPDIP4 TPDIN4
66 65 64 63 62 61 60 59
R21 15K
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8 RX1:1X4 RJ45X4 CN1A
TP3
GND
GND
TP4
RJ45X4
T3 1 2 1 2 16 15 13 12 10 9 10 9 13 12 4 5 7 8 TD01-0756K 16 15 4 5 7 8
1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 P1 DB15 GND |LINK |12PORT2.SCH |12PORT3.SCH |12PORT4.SCH
Figure 6. 12-Port Application Schematic, 68-Pin PLCC Package (Sheet 1 of 4)
1 2 3 4 5 6 7 8
When used with an EPROM, pin 17 of LXT914 (U1) may require either a 4.7k pull-up (LEDMO High) or a 4.7k pull-down (LEDMOWasson Low). Refer to Level One Communications / Stephen D. Table 14 for details. 9750 Goethe Road
Sacramento, CA 95827 916-854-1185 Phone 916-854-1102 Fax Title 12 Port HUB Application Size B Document Number R
Datasheet
U3 15 17 18 14 16 SENO* RTS/SDO/LEDM0 SCLKIO CS/SENI* SDI A/SYNC* LOC/EXT* VCC SYSCLK BCLKIO RESET LEDM1 TEST 120pF C11 C13 RBIAS 120pF T5 120pF LEDCF LEDJM/AUISEL C12 CN2D 27 28 12 13 IRENA* IRDAT IRDEN* IRCFS* IRCOL* 4 5 6 7 8
Datasheet
IRENA IRDAT IRCFS IRCOL 11 10 20 35 19 37 12.4K R39 1% LEDAUI LEDTP1 LEDTP2 LEDTP3 LEDTP4 BNCLED TP5LED TP6LED TP7LED TP8LED 33 29 30 31 32 GND 1 2 3 4 5 6 7 8 RJ45X4 CN2C 16 15 14 13 12 11 10 9
SENO2
SCLKIO SENO1 SDIN
CLK20 CLK10
RESET
TP5
21 22 23 24 25 SECTP1/DSQE SECTP2 SECTP3 SECTP4 FPS/SECAUI TPDOP1 TPDON1 TPDOP2 TPDON2 TPDOP3 TPDON3 TPDOP4 TPDON4 C14 56 57 54 53 50 51 48 47
GND
R27 R28 R29 R30 R31 R32 R33 R34
24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9
1% 1% 1% 1% 1% 1% 1% 1%
1 2 3 4 5 6 7 8
1 : 1 . 41 TX1:1.41X4
TP6
RJ45X4 CN2B
R26 120pF T4 R23 100 1% 100 1%
R36 78.7 1% LXT914 R24 100 1% R25 100 1%
40 41 42 43 44 45 AUIDOP AUIDON AUIDIP AUIDIN AUICIP AUICIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 TPDIP4 TPDIN4
66 65 64 63 62 61 60 59
1 2 3 4 5 6 7 8
TP7
RJ45X4 CN2A
1:1 RX1:1X4
1 2 3 4 5 6 7 8
R37 78.7 1% R38 78.7 1%
TP8
RJ45X4
U4 2 1 CDCD+ DIDI+ DODO+ N/C 12 RXI TXO 18 17 CDS 4 3 6 5 VCC 9 VCC SQE DISABLED 11 GND MD-001 C9 .75uF 1KV R35 1M 1/2W C8 .01uF 500V Level One Communications VEE HBE 10 C10 .1uF C7 10uF 16v 16 20
1 2 3 4 5 6 7 8
LOCATE MD-001 AS CLOSE AS POSSIBLE TO BNC
Figure 6. 12-Port Application Schematic, 68-Pin PLCC Package (Sheet 2 of 4)
J1 BNC
PLACE CAPS CLOSE TO MD-001 GND GND Title
9750 Goethe Road Sacramento, CA 95827 916-854-1185 Phone 916-854-1102 Fax
12 Port HUB Application Size B Date: May 5, 1995 Sheet 2 of 4 Document Number REV 1
Flexible Quad Ethernet Repeater -- LXT914
A8323-01
31
32
IRENA IRDAT IRCFS IRCOL
TP9LED
D1 1 3 PUP1 PUP2 PUP3 4 3 4 2 1 2 D3 PDN1 PDN2 PDN3
TP10LED
DUAL LED RP1
DUAL LED
VCC RP3 1
U5 TOP GREEN BOTTOM RED 470 15 17 18 14 16 SENO* RTS/SDO/LEDM0 SCLKIO CS/SENI* SDI A/SYNC* LOC/EXT* VCC D4 1 1 3 4 RP2 820 2 3 4 2 8765432 D2 SYSCLK BCLKIO RESET LEDM1 TEST DUAL LED 1 T7 GND DUAL LED RBIAS LEDCF LEDJM/AUISEL 27 28 12 13 IRENA* IRDAT IRDEN* IRCFS* IRCOL* 4 5 6 7 8
8 9 10 11 12 13 14 2 3 4 5 6 7 8
7 6 5 4 3 2 1
SCLKIO SENO2 SDIN
C15 .1uF GND 820
TP11LED
TP12LED
CLK20 CLK10 20 35 19 37 LEDAUI LEDTP1 LEDTP2 LEDTP3 LEDTP4
11 10
RESET
CN3D
LXT914 -- Flexible Quad Ethernet Repeater
GND
12.4K R52
1%
33 29 30 31 32
1 2 3 4 5 6 7 8 RJ45X4 CN3C
TP9
21 22 23 24 25 SECTP1/DSQE SECTP2 SECTP3 SECTP4 FPS/SECAUI R44 R45 R46 R47 R48 R49 R50 R51 1 2 3 4 5 6 7 8 C16 C17 C18 C19 TX1:1.41X4 120pF T6 120pF 120pF 120pF 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 1% 1% 1% 1% 1% 1% 1% 1%
GND
TPDOP1 TPDON1 TPDOP2 TPDON2 TPDOP3 TPDON3 TPDOP4 TPDON4
56 57 54 53 50 51 48 47
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8 RJ45X4 CN3B
TP10
40 41 42 43 44 45 AUIDOP AUIDON AUIDIP AUIDIN AUICIP AUICIN R40 100 1% LXT914 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 R43 100 1%
TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 TPDIP4 TPDIN4
66 65 64 63 62 61 60 59
TP11
RJ45X4 CN3A
R41 100 1% R42 100 1% RX1:1X4
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 RJ45X4
TP12
Figure 6. 12-Port Application Schematic, 68-Pin PLCC Package (Sheet 3 of 4)
Level One Communications 105 Lake Forest Way Folsom, CA 916-985-3670 Voice 916-985-3512 Fax Title Ports 9-12 Size B Date: May 5, 1995 Sheet 3 of 4 Document Number REV 1
A8324-01
Datasheet
VCC RP5 1 RP4 RP6
LED OPERATION TABLE
Datasheet
TP# LINK TX POL RX PART C20 .1uF 1 820 GND 470 820 GND AUI/BNC RX JAB TX RX COL RX PART 8 7 6 5 4 3 2 8 9 10 11 12 13 14 2 3 4 5 6 7 8 7 6 5 4 3 2 1 D5 TOP GREEN BOTTOM RED 1 D12 3 4 2 PDN1
SOLID TOP BLINKING TOP ALTERNATING TOP/BOT BLINKING BOTTOM SOLID BOTTOM
AUI TP6LED
TP6LED DUAL LED D6 TOP GREEN BOTTOM RED 1 3 4 2 D13 3 4 TOP GREEN BOTTOM RED 1 2 DUAL LED
AUILED
PUP1
PDN2
BNC TP7LED
TP7LED 3 TOP GREEN BOTTOM RED 1 DUAL LED
BNCLED
2 4 PUP2 DUAL LED
D7 TOP GREEN BOTTOM RED 1 3 4 2 D14
PDN3
TP1LED TP8LED
TP8LED DUAL LED
TP1LED
TOP GREEN BOTTOM RED
1 3
2 4 PUP3 DUAL LED
D8 TOP GREEN BOTTOM RED 1 3 4 2 BOTTOM RED 1 3 D15 2 R53 4 820 DUAL LED D9 TOP GREEN BOTTOM RED 1 3 4 2
TP2LED COL
COLLED DUAL LED
TP2LED
VCC
TP3LED
DUAL LED
TP3LED
D10 TOP GREEN BOTTOM RED 1 3 4 2
TP4LED
DUAL LED
TP4LED
D11 Level One Communications 1 3 4 2 9750 Goethe Road Sacramento, CA 95827 916-854-1185 Phone 916-854-1102 Fax Title 12 Port HUB Application Size B Date: May 5, 1995 Sheet 4 of 4 Document Number REV 1 TOP GREEN BOTTOM RED
TP5LED
DUAL LED
Figure 6. 12-Port Application Schematic, 68-Pin PLCC Package (Sheet 4 of 4)
TP5LED
Flexible Quad Ethernet Repeater -- LXT914
A8325-01
33
34
COLLISION VCC 510 R18 VCC VCC D2 R15 330 510 R23 D3 link2 irena irdat 510 R22 D4 link3 510 R21 D5 link4 510 R20 CN1D ircfs ircol U1 15 17 18 14 16 SENO* RTS/SDO/LEDM0 SCLKIO CS/SENI* SDI A/SYNC* LOC/EXT* 27 28 12 13 IRENA* IRDAT IRDEN* IRCFS* IRCOL* 4 5 6 7 8 R19 1K R14 330 R16 330 1% R13 330 link1 Green LEDs D1 YELLOW LED 11 10 SYSCLK BCLKIO RESET LEDM1 TEST RBIAS T2 C2 120pf C3 120pf LEDCF LEDJM/AUISEL 20 35 19 37 1% LEDAUI LEDTP1 LEDTP2 LEDTP3 LEDTP4 33 29 30 31 32
LED Mode 1 Selected
Y1
8 OUT 20MHz_OSC
20MHz BCLKIO
RESET
TP1
RJ45X4 CN1C
12.4K R17 21 22 23 24 25 SECTP1/DSQE SECTP2 SECTP3 SECTP4 FPS/SECAUI TPDOP1 TPDON1 TPDOP2 TPDON2 TPDOP3 TPDON3 TPDOP4 TPDON4 C4 120pf C5 120pf TX1:1.41X4 TG54-1006N2 56 57 54 53 50 51 48 47 R5 R6 R7 R8 R9 R10 R11 R12 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 1% 1% 1% 1% 1% 1% 1% 1%
1 2 3 4 5 6 7 8
LXT914 -- Flexible Quad Ethernet Repeater
VCC
1 2 3 4 5 6 7 8 RJ45X4
TP2
40 41 42 43 44 45 AUIDOP AUIDON AUIDIP AUIDIN AUICIP AUICIN R4 R1 T1 100 1% 100 1% LXT914PC
TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 TPDIP4 TPDIN4
66 65 64 63 62 61 60 59
CN1B
R2 100 1% R3 100 1%
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9 RX1:1X4 TG01-1006N2
1 2 3 4 5 6 7 8 RJ45X4 CN1A
TP3
|LINK |PAGE2.SCH
1 2 3 4 5 6 7 8 RJ45X4
TP4
Figure 7. 8-Port Application Schematic, LED Mode 1 with AUISEL = MAU (Sheet 1 of 2)
Level One Communications / Stephen D. Wasson 9750 Goethe Road Sacramento,CA 95827 Phone 916-854-1185 FAX 916-854-1102 Title 8 Port File Server Application Size Document Number B Date: June 23, 1995 Sheet
A8326-01
Datasheet
1
of
REV 2
Datasheet
LED Mode 1 Selected
Green LEDs D6 510 R42 LINK6 irena irdat 510 R43 LINK7 510 R44 LINK8 1K R41 C6 120pf C7 120pf 510 R45 CN2D D9 D8 ircfs ircol IRENA* IRDAT IRDEN* IRCFS* IRCOL* A/SYNC* LOC/EXT* SYSCLK BCLKIO RESET LEDM1 TEST RBIAS T3 LEDCF LEDJM/AUISEL 27 28 12 13 4 5 6 7 8 D7 VCC LINK5 VCC R23 1K U2 15 17 18 14 16 SENO* RTS/SDO/LEDM0 SCLKIO CS/SENI* SDI
VCC
D10 1N4148 C1 .1uF 20MHz BCLKIO RESET 35 19 R24 15K 37 12.4K R28 1% LEDAUI LEDTP1 LEDTP2 LEDTP3 LEDTP4 20 11 10
RESET
33 29 30 31 32
1 2 3 4 5 6 7 8 RJ45X4 CN2C
TP5
VCC
21 22 23 24 25 SECTP1/DSQE SECTP2 SECTP3 SECTP4 FPS/SECAUI TPDOP1 TPDON1 TPDOP2 TPDON2 TPDOP3 TPDON3 TPDOP4 TPDON4 R32 R29 C8 120pf T4 100 1% 100 1% C9 120pf TX1:1.41X4 TG54-1006N2 56 57 54 53 50 51 48 47 R33 R34 R35 R36 R37 R38 R39 R40 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 1% 1% 1% 1% 1% 1% 1% 1% 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8 RJ45X4 CN2B
TP6
40 41 42 43 44 45 AUIDOP AUIDON AUIDIP AUIDIN AUICIP AUICIN LXT914PC R30 100 1% R31 100 1% 1 2 3 4 5 6 7 8 R25 78.7 1%
AUI Port
16 15 13 12 R27 78.7 1% R26 78.7 1% 13 12
TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 TPDIP4 TPDIN4 16 15 14 13 12 11 10 9 RX1:1X4 TG01-1006N2
66 65 64 63 62 61 60 59
1 2 3 4 5 6 7 8 RJ45X4 CN2A
TP7
DIP DIN
1 2
T5 1 16 2 15
DOP DON
4 5
4 5
CIP CIN
7 8
10 7 10 9 8 9 TG01-0756
1 2 3 4 5 6 7 8 RJ45X4
TP8
AUISEL = MAU
Level One Communications 9750 Goethe Road Sacramento, CA 95827 Title Size B Date: 8 Port File Server Application Document Number June 20, 1995 Sheet 2 of REV 2
Figure 7. 8-Port Application Schematic, LED Mode 1 with AUISEL = MAU (Sheet 2 of 2)
Flexible Quad Ethernet Repeater -- LXT914
A8327-01
35
LXT914 -- Flexible Quad Ethernet Repeater
4.0
Note:
Test Specifications
Minimum and maximum values in Tables 20 through 28, and Figures 8 and 9 represent the performance specifications of the LXT914 and are guaranteed by test except, where noted, by design.
Table 20. Absolute Maximum Ratings
Parameter Supply voltage LXT914PC/QC Operating temperature LXT914PE Storage temperature TOP TST -40 -65 - - +85 +150 C C Symbol VCC TOP Min -0.3 0 Typ - - Max 6 +70 Units V C
Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 21. Recommended Operating Conditions
Parameter Recommended supply voltage LXT914PC/QC Recommended operating temperature LXT914PE TOP -40 - +85 C Symbol VCC TOP Min 4.75 0 Typ 5.0 - Max 5.25 +70 Units V C
Table 22. I/O Electrical Characteristics1 (over recommended range)
Parameter Supply current Input Low voltage Input Low voltage (RESET) Input High voltage Input High voltage (RESET) Output Low voltage Output Low voltage Output Low voltage (LED) Output High voltage Output High voltage Output High voltage (LED) Input Low current Symbol ICC VIL VILRESET VIH VIHRESET VOL VOL VOLL VOH VOH VOHL IIL Min - - - 2.0 4.0 - - - 2.4 90 4 - Typ2 - - - - - - - - - - - - Max 180 0.8 0.8 - - 0.4 10 1.0 - - - 2 Units mA V V V V V % VCC V V % VCC V mA VCC = 4.75 V IOL = 1.6 mA IOL < 10 A IOLL = 5 mA IOH = 40 A IOH < 10 A IOHL = -5 mA VOL = .4 V VCC = 5.25 V Test Conditions
NOTES: 1. Not applicable to IRB signals. IRB electrical characteristics are specified in Table 25. 2. Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing.
36
Datasheet
Flexible Quad Ethernet Repeater -- LXT914
Table 22. I/O Electrical Characteristics1 (over recommended range)
Parameter Output rise / fall time RESET pulse width RESET fall time Symbol - PWRESE
T
Min - 1.0 -
Typ2 3 - -
Max 8 - 20.0
Units ns ms
Test Conditions CLOAD = 20 pF VCC = 4.75 V VIHRESET to VILRESET
TFRESET
s
NOTES: 1. Not applicable to IRB signals. IRB electrical characteristics are specified in Table 25. 2. Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing.
Table 23. AUI Electrical Characteristics (over recommended range)
Parameter Input Low current Input High current Differential output voltage Receive input impedance Differential squelch threshold Symbol IIL IIH VOD ZIN VDS Min - - 550 - - Typ - - - 20 220 Max -700 500 1200 - - Units Test Conditions
A A
mV k mV Between CIP/CIN & DIP/ DIN
Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing.
Table 24. Twisted-Pair Electrical Characteristics (over recommended range)
Parameter Transmit output impedance Peak differential output voltage Transmit timing jitter addition Transmit timing jitter added by the MAU and PLS sections2 Receive input impedance Differential squelch threshold (Normal threshold: ERSQx = 0) Differential squelch threshold (Reduced threshold: ERSQx = 1) Symbol ZOUT VOD - - ZIN VDS VDSL Min - 3.3 - - - 300 180 Typ1 5 3.5 6.4 3.5 20 420 250 Max - 3.7 10 5.5 - 565 345 Units Test Conditions
V ns ns k mV mV Load = 100 at TPOP and TPON 0 line length After line model specified by IEEE 802.3 for 10BASE-T Between TPIP/TPIN 5 MHz square wave input 5 MHz square wave input
NOTES: 1. Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing. 2. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU.
Datasheet
37
LXT914 -- Flexible Quad Ethernet Repeater
Table 25. IRB Electrical Characteristics (over recommended range)
Parameter Output Low voltage Output rise or fall time Input Low voltage: IRENA, IRCOL & IRDAT Input High voltage: IRENA, IRCOL & IRDAT Input Low voltage: BCLKIO Input High voltage: BCLKIO Symbol VOL TF VILIRB VIHIRB VILBCLK VIHBCLK Min - - - 3.0 - 4.0 Typ .3 4 - - - - Max .6 12 0.8 - 0.4 - Units V ns V V V V RL = 330 RL = 330 RL = 330 RL = 330 Test Conditions
Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing.
Table 26. Switching Characteristics (over recommended range)
Parameter Maximum transmit time Jabber Timing Unjab time Time link loss Link Integrity Timing Time between Link Integrity Pulses Interval for valid receive Link Integrity Pulses - - 10 4.1 9.6 60 - - - - 20 30 Min 5.0 Typ - Max 5.5 Units ms
s
ms ms ms
Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing.
Table 27. Serial Port Timing--External Mode (over recommended range)
Parameter SCLKIO High to SENI Low (active) SCLKIO High to SDIN data valid SCLKIO High to SENO Low (active) SCLKIO Low to SDOUT data valid Symbol tS1 tS2 tS3 tS4 Minimum 0 0 5 5 Typical - - - - Maximum 50 50 15 15 Units ns ns ns ns
Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing.
38
Datasheet
Flexible Quad Ethernet Repeater -- LXT914
Figure 8. Serial Port Timing
SCLKIO
RESET
tS1
SENI
tS2
SDIN
tS3
SENO
tS4
1 SDOUT 2 3 4 5 6 48
Table 28. Inter-Repeater Bus Timing (over recommended range)
Parameter Start of Frame to IRDEN Low (active) Start of Frame to IRENA Low (active) BCLKIO to IRDAT valid (Synchronous mode) BCLKIO to IRDAT valid (Asynchronous mode) IRENA Low (active) to TP outputs active IRENA Low (active) to AUI output active End of Frame clock to IRENA High (inactive) IRENA High (inactive) to IRDEN High (inactive) IRENA High (inactive) to TP outputs inactive IRENA High (inactive) to AUI output inactive Symbol tIRB1 tIRB2 tIRB3 tIRB3 tIRB4 tIRB5 tIRB6 tIRB7 tIRB8 tIRB9 Minimum 10 125 5 - 525 475 5 95 575 425 Typical - - - 50 - - - - - - Maximum 150 225 30 - 600 525 30 105 600 450 Units ns ns ns ns ns ns ns ns ns ns
Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing.
Datasheet
39
LXT914 -- Flexible Quad Ethernet Repeater
Figure 9. Inter-Repeater Bus Timing
Rx DATA tIRB4 TPs tIRB5 AUI tIRB9 tIRB7 tIRB1 IRDEN tIRB2 IRENA tIRB3 IRDAT tIRB6 tIRB8
BCLKIO
40
Datasheet
Flexible Quad Ethernet Repeater -- LXT914
5.0
Mechanical Specifications
Figure 10. LXT914PC/PE Package Specifications 68-Pin Plastic Leaded Chip Carrier
* Part Number LXT914PC for Commercial Temperature Range (0C to +70C) * Part Number LXT914PE for Extended Temperature Range (-40C to +85C)
Inches Dim Min A A1 A2 B C D D1 F 0.165 0.090 0.062 0.050 0.026 0.985 0.950 0.013 Max 0.180 0.120 0.083 - 0.032 0.995 0.958 0.021 Min 4.191 2.286 1.575 1.270 0.660 25.01 9 24.13 0 0.330 Max 4.572 3.048 2.108 - 0.813 25.27 3 24.33 3 0.533
D1 D D A2 A1 F A B C
Millimeters
C L
Datasheet
41
LXT914 -- Flexible Quad Ethernet Repeater
Figure 11. LXT914QC Package Specifications 100-Pin Quad Flat Package
* Part Number LXT914QC * Commercial Temperature Range (0C to +70C)
Inches Dim Min A A1 A2 B D D1 D3 E E1 E3 e L L1 - 0.010 0.100 0.009 0.931 0.783 Max 0.134 - 0.120 0.015 0.951 0.791 Min - 0.25 2.55 0.22 23.65 19.90 Max 3.40 - 3.05 0.38 24.15 20.10 Millimeters
D D1
E1
E
0.742 REF 0.695 0.547 0.715 0.555
18.85 REF 17.65 13.90 18.15 14.10
0.486 REF 0.026 BSC (nominal) 0.026
12.35 REF 0.65 BSC (nominal) 0.65 0.95
0.037
D Side pin count = 30 E Side pin count = 20
e/
0.077 REF 0 5 7 16
1.95 REF 0 5 7 16
3
e
2
BSC = Basic Spacing Between Centers
3 L1 A A2 A1 L B 3
42
Datasheet

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